A Voltage Scalable 0 . 26 V , 64 kb 8 T SRAM With V � Lowering Techniques and Deep Sleep Mode
نویسندگان
چکیده
A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design improves cell write margin and read performance without the aid of peripheral circuits. A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a read current at subthreshold supply voltages. The MBLC allows us to lower to 0.26 V and also eliminates the need for precharged read bitlines. A floating read bitline and write bitline scheme reduces the leakage power consumption. A deep sleep mode minimizes the standby leakage power consumption without compromising the hold mode cell stability. Finally, an automatic wordline pulse width control circuit tracks PVT variations and shuts off the bitline leakage current upon completion of a read operation.
منابع مشابه
A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep mode
A voltage scalable 0.26V, 64kb 8T SRAM with 512 cells per bitline is implemented in a 130nm CMOS process. Reverse short channel effect was utilized to improve cell write margin and read performance. A marginal bitline leakage compensation scheme was used during read operation to lower Vmin down to 0.26V. Floating write bitline and read bitline, auto wordline pulse width control, and a deep slee...
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